Performance Analysis of the Algorithms for the Construction of Rectilinear Steiner Minimum Tree

The advances in VLSI technology have led to complex and larger circuits. As the circuits become complex and large, the amount of time required for the design of such circuits increases. The people in the VLSI industry are looking for faster EDA (Electronic Design Automation) tools so as to reduce the design time. Routing is a phase in the design (physical design) of electronic circuits, wherein pins of a net will be interconnected and this uses Rectilinear Steiner Minimum Trees. Rectilinear Steiner Minimum Tree problem is to find a minimum length tree connecting the given set of points using only horizontal and vertical line segments, with the additional set of points (Steiner points). Steiner points are introduced to reduce the total length of the tree and to connect in rectilinear manner. The problem of finding Rectilinear Steiner Minimum Tree is one of the fundamental problems in the field of electronic design automation. This paper provides a comprehensive analysis of the various Rectilinear Steiner Minimum Tree algorithms proposed till date and shows that there is a need for an algorithm or approach to produce better solution quality (reduced wire length) in less time. Rectilinear Steiner Minimum Tree is widely used in global routing phase of VLSI design and wire length estimation.